1. Field of the Invention
The present invention relates to a semiconductor device that incorporates a dynamically reconfigurable circuit technology, and also to a method of processing data by such a semiconductor device.
2. Description of the Related Art
The recent trend of small-dimension low-power-consumption devices such as cellular phones has been toward more complicated and diversified functions, and high performance has been demanded for such devices. To achieve both high-performance and small-dimension low-power-consumption features, the hardware needs to be specially developed and manufactured. As the complication and diversification of the functions proceeds, however, the costs of developing and manufacturing such hardware are increasing every year. As an option to reduce the development and manufacturing costs, a semiconductor device incorporating the dynamically reconfigurable circuit technology has been receiving attention.
A semiconductor device using the dynamically reconfigurable circuit technology includes reconfigurable circuits, such as FPGAs, and a memory device that stores therein various items of circuit information necessary to construct different circuits (hereinafter, “execution circuits”) that are to be executed by the circuit reconfigurable circuits. The semiconductor device of this type reads necessary circuit information and constructs an execution circuit under operating conditions, in accordance with rules predetermined by a software program or the like. Such a device is different from a conventional semiconductor device with a FPGA in that execution circuits can be changed during the operation.
With the semiconductor device using the dynamically reconfigurable circuit technology, the cost of developing the specially designed hardware can be reduced in the same level as the FPGA. Furthermore, the cost of manufacturing the specially designed hardware can also be reduced because various functions can be realized on a small semiconductor device by dynamically constructing execution circuits.
Examples of semiconductor devices using the dynamically reconfigurable circuit technology include a Dynamically Reconfigurable Processor (DRP, see “Reconfigurable System”, Ohmsha, pp. 189-208) offered by NEC Electronics and a device described in JP-A 2007-257549 (KOKAI).
The DRP offered by NEC Electronics is configured in such that processing elements (PEs), which are fundamental computing elements, are aligned in two-dimensional array, with a state transition controller positioned at the center thereof. A PE is a computing device that constitutes an execution circuit and stores different items of circuit information regarding types of computation and connections with other PEs in an instruction memory provided inside the PE. Each of the PEs reads the circuit information from the instruction memory in accordance with an instruction pointer given by the state transition controller, and dynamically constitutes an execution circuit.
According to JP-A 2007-257549 (KOKAI), a controller that controls the changes of the configuration and computing units that perform computations are connected to one another in the form of a pipeline. A reconfiguration rule is supplied from the controller to change the execution circuit, with one of the computing units receiving the rule first and the rest of the units successively receiving the rule one cycle after the previous unit of each unit. Then, each of the computing units reads the circuit information from its inner memory in accordance with the reconfiguration rule received in the corresponding cycle, and dynamically constitutes an execution circuit.
To achieve a high-performance semiconductor device incorporating the dynamically reconfigurable circuit technology, it is necessary to reduce the non-computing time and thereby maximize the amount of computation performed at the computing elements within a limited period of time.
In a DRP, however, an instruction pointer is supplied from the state transition controller to all the PEs at the same time, in accordance with which each of the PEs starts constituting an execution circuit at the time. Thus, when some of the PEs have completed the computation but some others have not, the execution circuit of any PE in the computing process should not be changed, and therefore none of the execution circuits of the PEs is allowed to change. As a result, the period of non-computing time becomes longer.
According to JP-A 2007-257549 (KOKAI), the reconfiguration rule supplied by the controller sequentially reaches the computing units with a one-cycle lag between the units, and each of the computing units constitutes an execution circuit in accordance with the reconfiguration rule received in the corresponding cycle. Thus, even if the controller supplies a reconfiguration rule to an upper one of the pipeline-connected computing units to change an execution circuit before the lower computing units finish the computations, accurate computation results can be obtained as long as the lower units finish the computations before the reconfiguration rule reaches these units. Hence, the non-computing time becomes shorter than in the DRP.
According to the description of JP-A 2007-257549 (KOKAI), however, the reconfiguration rule is always transferred from the topmost controller of the pipeline to the lower computing units, one in a cycle. This means that, when the number of computations that are to be performed on data is larger than the number of stages of computing units, midstream results output by the lowermost computing unit needs to be input to the uppermost computing unit to newly perform the computations in sequence from the uppermost computing unit down. If the number of computations re-starting from the uppermost computing unit is smaller than the number of computing units, a non-computing time is generated at the lower computing units.